simd: riscv: implement RVV intrinsics #9731
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Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
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patrick-stephens
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This is because RVV's instruction set is not having a fixed length. Instead, RVV needs to specify the VLEN for the width of vectorized calcucaltion. In this case, we assumed as 128 for VLEN. Signed-off-by: Hiroshi Hatake <[email protected]>
Signed-off-by: Hiroshi Hatake <[email protected]>
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In RISC-V intrinsics, RVV (RISC-V "Vector") extensions are existing.
In this PR, I experimented to implement RVV extensions and got succeeded to pass internal and runtime tests with turning on this RVV extensions.
This PR uses RVV v0.11 intrinsics.
Some of the RVV extensions are not corresponding one-by-one to NEON or SSE2.
Plus,
vuint8m1_tandvuint32m1_ttypes do not have fixed size.So, I assumed the fixed lengths for them is 16 like as the result of
sizeof(__m128i)orsizeof(uint8x16_t).Also, we define that
FLB_SIMD_VEC8_INST_LENmacro as an emulation for aligned behavior against SSE2 or NEON.For non-RVV, it just replaces with sizeof(flb_vector8). However, in RVV, gcc complains that there is no sized attributes for
vuint8m1_ttype.So, we define the alternative fixed size to determine the length of RVV's instruction set.
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[N/A]in the box, if an item is not applicable to your change.Testing
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If this is a change to packaging of containers or native binaries then please confirm it works for all targets.
ok-package-testlabel to test for all targets (requires maintainer to do).Documentation
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